.autoimport
A96F928N EQU 1
.include "sysdef16.inc"
ccounter equ pr1
.stabs "icc_compiled.",60,0,0,0
.stabs "D:\YKS4509N-A96F928N V1.2\Interrupt.c",100,0,3,0
.stabs "int:t1=r1;-128;127;",128,0,0,0
.stabs "char:t2=r2;-128;127;",128,0,0,0
.stabs "double:t3=r1;3;0;",128,0,0,0
.stabs "float:t4=r1;3;0;",128,0,0,0
.stabs "long double:t5=r1;3;0;",128,0,0,0
.stabs "long:t6=r1;-2147483648;2147483647;",128,0,0,0
.stabs "long long:t7=r1;-2147483648;2147483647;",128,0,0,0
.stabs "short:t8=r1;-32768;32767;",128,0,0,0
.stabs "signed char:t9=r1;-128;127;",128,0,0,0
.stabs "unsigned char:t10=r1;0;255;",128,0,0,0
.stabs "unsigned long:t11=r1;0;4294967295;",128,0,0,0
.stabs "unsigned long long:t12=r1;0;4294967295;",128,0,0,0
.stabs "unsigned short:t13=r1;0;65535;",128,0,0,0
.stabs "unsigned int:t14=r1;0;255;",128,0,0,0
.stabs "void:t15=15",128,0,0,0
.stabs "bit:t16=r16;0;1;",128,0,0,0
public _ALLint
public ALLint_bp
.section ".code"
.stabs "ALLint:F15",36,0,0,_ALLint
.section ".S0",C_CODE
.SYMDEF ".S0" INT:-1
_ALLint:
.SYMDEF "_ALLint" INT:-1
.stabn 192,0,0,L17
L17:
.stabn 68,0,15,L19
L19:
.stabn 68,0,16,L20
L20:
LDA _IntVecIdx,0,0
mov ecx,a
EQNEPRIB ecx,3
jbc STATUS,zf
EXTJMP @L$4
EQNEPRIB ecx,9
jbc STATUS,zf
EXTJMP @L$3
EQNEPRIB ecx,49
jbc STATUS,zf
EXTJMP @L$12
EQNEPRIB ecx,61
jbc STATUS,zf
EXTJMP @L$13
EQNEPRIB ecx,63
jbc STATUS,zf
EXTJMP @L$3
jmp @L$2
.stabn 192,0,1,L21
L21:
.stabn 68,0,17,L22
L22:
L$4:
.stabn 68,0,19,L23
L23:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(19):"
DISI
.stabn 68,0,19,L24
L24:
.stabn 68,0,23,L25
L25:
jbs _EXSF0,2
EXTJMP @L$5
.stabn 192,0,2,L26
L26:
.stabn 68,0,24,L27
L27:
.stabn 68,0,25,L28
L28:
jbs _mandatory_net,BIT
EXTJMP @L$7
.stabn 192,0,3,L29
L29:
.stabn 68,0,26,L30
L30:
.stabn 68,0,27,L31
L31:
mov a,@1
mov Delay_nms_bp+0,a
.STACK Delay_nms_bp,parameter,1
call _Delay_nms
.stabn 68,0,28,L32
L32:
.stabn 224,0,3,L33
L33:
jmp @L$8
L$7:
.stabn 192,0,3,L34
L34:
.stabn 68,0,30,L35
L35:
.stabn 68,0,31,L36
L36:
call _KEY_INT_Det
.stabn 68,0,32,L37
L37:
.stabn 224,0,3,L38
L38:
L$8:
.stabn 68,0,33,L39
L39:
.stabn 224,0,2,L40
L40:
L$5:
.stabn 68,0,38,L41
L41:
jbs _EXSF1,3
EXTJMP @L$9
.stabn 192,0,2,L42
L42:
.stabn 68,0,39,L43
L43:
.stabn 68,0,44,L44
L44:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L45
L45:
.stabn 68,0,44,L46
L46:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L47
L47:
.stabn 68,0,44,L48
L48:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L49
L49:
.stabn 68,0,44,L50
L50:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L51
L51:
.stabn 68,0,44,L52
L52:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L53
L53:
.stabn 68,0,44,L54
L54:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L55
L55:
.stabn 68,0,44,L56
L56:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L57
L57:
.stabn 68,0,44,L58
L58:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L59
L59:
.stabn 68,0,44,L60
L60:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L61
L61:
.stabn 68,0,44,L62
L62:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L63
L63:
.stabn 68,0,44,L64
L64:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L65
L65:
.stabn 68,0,44,L66
L66:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L67
L67:
.stabn 68,0,44,L68
L68:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L69
L69:
.stabn 68,0,44,L70
L70:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L71
L71:
.stabn 68,0,44,L72
L72:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L73
L73:
.stabn 68,0,44,L74
L74:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L75
L75:
.stabn 68,0,44,L76
L76:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L77
L77:
.stabn 68,0,44,L78
L78:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L79
L79:
.stabn 68,0,44,L80
L80:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L81
L81:
.stabn 68,0,44,L82
L82:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(44):"
nop
.stabn 68,0,44,L83
L83:
.stabn 68,0,45,L84
L84:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L85
L85:
.stabn 68,0,45,L86
L86:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L87
L87:
.stabn 68,0,45,L88
L88:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L89
L89:
.stabn 68,0,45,L90
L90:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L91
L91:
.stabn 68,0,45,L92
L92:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L93
L93:
.stabn 68,0,45,L94
L94:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L95
L95:
.stabn 68,0,45,L96
L96:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L97
L97:
.stabn 68,0,45,L98
L98:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L99
L99:
.stabn 68,0,45,L100
L100:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L101
L101:
.stabn 68,0,45,L102
L102:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L103
L103:
.stabn 68,0,45,L104
L104:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L105
L105:
.stabn 68,0,45,L106
L106:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L107
L107:
.stabn 68,0,45,L108
L108:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L109
L109:
.stabn 68,0,45,L110
L110:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L111
L111:
.stabn 68,0,45,L112
L112:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L113
L113:
.stabn 68,0,45,L114
L114:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L115
L115:
.stabn 68,0,45,L116
L116:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L117
L117:
.stabn 68,0,45,L118
L118:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L119
L119:
.stabn 68,0,45,L120
L120:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L121
L121:
.stabn 68,0,45,L122
L122:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(45):"
nop
.stabn 68,0,45,L123
L123:
.stabn 68,0,46,L124
L124:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L125
L125:
.stabn 68,0,46,L126
L126:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L127
L127:
.stabn 68,0,46,L128
L128:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L129
L129:
.stabn 68,0,46,L130
L130:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L131
L131:
.stabn 68,0,46,L132
L132:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L133
L133:
.stabn 68,0,46,L134
L134:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L135
L135:
.stabn 68,0,46,L136
L136:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L137
L137:
.stabn 68,0,46,L138
L138:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L139
L139:
.stabn 68,0,46,L140
L140:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L141
L141:
.stabn 68,0,46,L142
L142:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L143
L143:
.stabn 68,0,46,L144
L144:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L145
L145:
.stabn 68,0,46,L146
L146:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L147
L147:
.stabn 68,0,46,L148
L148:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L149
L149:
.stabn 68,0,46,L150
L150:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L151
L151:
.stabn 68,0,46,L152
L152:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L153
L153:
.stabn 68,0,46,L154
L154:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L155
L155:
.stabn 68,0,46,L156
L156:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L157
L157:
.stabn 68,0,46,L158
L158:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L159
L159:
.stabn 68,0,46,L160
L160:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L161
L161:
.stabn 68,0,46,L162
L162:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(46):"
nop
.stabn 68,0,46,L163
L163:
.stabn 68,0,47,L164
L164:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L165
L165:
.stabn 68,0,47,L166
L166:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L167
L167:
.stabn 68,0,47,L168
L168:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L169
L169:
.stabn 68,0,47,L170
L170:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L171
L171:
.stabn 68,0,47,L172
L172:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L173
L173:
.stabn 68,0,47,L174
L174:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L175
L175:
.stabn 68,0,47,L176
L176:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L177
L177:
.stabn 68,0,47,L178
L178:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L179
L179:
.stabn 68,0,47,L180
L180:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L181
L181:
.stabn 68,0,47,L182
L182:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L183
L183:
.stabn 68,0,47,L184
L184:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L185
L185:
.stabn 68,0,47,L186
L186:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L187
L187:
.stabn 68,0,47,L188
L188:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L189
L189:
.stabn 68,0,47,L190
L190:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L191
L191:
.stabn 68,0,47,L192
L192:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L193
L193:
.stabn 68,0,47,L194
L194:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L195
L195:
.stabn 68,0,47,L196
L196:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L197
L197:
.stabn 68,0,47,L198
L198:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L199
L199:
.stabn 68,0,47,L200
L200:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L201
L201:
.stabn 68,0,47,L202
L202:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(47):"
nop
.stabn 68,0,47,L203
L203:
.stabn 68,0,48,L204
L204:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L205
L205:
.stabn 68,0,48,L206
L206:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L207
L207:
.stabn 68,0,48,L208
L208:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L209
L209:
.stabn 68,0,48,L210
L210:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L211
L211:
.stabn 68,0,48,L212
L212:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L213
L213:
.stabn 68,0,48,L214
L214:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L215
L215:
.stabn 68,0,48,L216
L216:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L217
L217:
.stabn 68,0,48,L218
L218:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L219
L219:
.stabn 68,0,48,L220
L220:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L221
L221:
.stabn 68,0,48,L222
L222:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L223
L223:
.stabn 68,0,48,L224
L224:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L225
L225:
.stabn 68,0,48,L226
L226:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L227
L227:
.stabn 68,0,48,L228
L228:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L229
L229:
.stabn 68,0,48,L230
L230:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L231
L231:
.stabn 68,0,48,L232
L232:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L233
L233:
.stabn 68,0,48,L234
L234:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L235
L235:
.stabn 68,0,48,L236
L236:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L237
L237:
.stabn 68,0,48,L238
L238:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L239
L239:
.stabn 68,0,48,L240
L240:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L241
L241:
.stabn 68,0,48,L242
L242:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(48):"
nop
.stabn 68,0,48,L243
L243:
.stabn 68,0,49,L244
L244:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L245
L245:
.stabn 68,0,49,L246
L246:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L247
L247:
.stabn 68,0,49,L248
L248:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L249
L249:
.stabn 68,0,49,L250
L250:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L251
L251:
.stabn 68,0,49,L252
L252:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L253
L253:
.stabn 68,0,49,L254
L254:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L255
L255:
.stabn 68,0,49,L256
L256:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L257
L257:
.stabn 68,0,49,L258
L258:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L259
L259:
.stabn 68,0,49,L260
L260:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L261
L261:
.stabn 68,0,49,L262
L262:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L263
L263:
.stabn 68,0,49,L264
L264:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L265
L265:
.stabn 68,0,49,L266
L266:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L267
L267:
.stabn 68,0,49,L268
L268:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L269
L269:
.stabn 68,0,49,L270
L270:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L271
L271:
.stabn 68,0,49,L272
L272:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L273
L273:
.stabn 68,0,49,L274
L274:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L275
L275:
.stabn 68,0,49,L276
L276:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L277
L277:
.stabn 68,0,49,L278
L278:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L279
L279:
.stabn 68,0,49,L280
L280:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L281
L281:
.stabn 68,0,49,L282
L282:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(49):"
nop
.stabn 68,0,49,L283
L283:
.stabn 68,0,51,L284
L284:
bc _flag_send_data,BIT
.stabn 68,0,52,L285
L285:
clr _r_code_bitcoun
.stabn 68,0,53,L286
L286:
bc _flag_rec_err,BIT
.stabn 68,0,54,L287
L287:
bs _Bus_task,BIT
.stabn 68,0,56,L288
L288:
mov a,@2
mov Delay_nms_bp+0,a
.STACK Delay_nms_bp,parameter,1
call _Delay_nms
.stabn 68,0,57,L289
L289:
call _The_Bus
.stabn 68,0,58,L290
L290:
LDA _count,0,0
add a,@1
STA _count,0,0
.stabn 68,0,59,L291
L291:
.stabn 224,0,2,L292
L292:
L$9:
.stabn 68,0,64,L293
L293:
bc _EXSF0,2
.stabn 68,0,65,L294
L294:
bc _EXSF1,3
.stabn 68,0,66,L295
L295:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(66):"
ENI
.stabn 68,0,66,L296
L296:
.stabn 68,0,67,L297
L297:
jmp @L$3
.stabn 68,0,69,L298
L298:
L$12:
.stabn 68,0,71,L299
L299:
bc _URSF,4
.stabn 68,0,72,L300
L300:
call _Rece_info
.stabn 68,0,73,L301
L301:
jmp @L$3
L$13:
.stabn 68,0,75,L302
L302:
UGTRIB _XS_count,0x8
jbs STATUS, cf
EXTJMP L$14
.stabn 192,0,2,L303
L303:
.stabn 68,0,76,L304
L304:
.stabn 68,0,77,L305
L305:
LDA _XS_count,0,0
add a,@1
STA _XS_count,0,0
.stabn 68,0,78,L306
L306:
.stabn 224,0,2,L307
L307:
jmp @L$15
L$14:
.stabn 192,0,2,L308
L308:
.stabn 68,0,80,L309
L309:
.stabn 68,0,81,L310
L310:
clr _XS_count
.stabn 68,0,82,L311
L311:
.stabn 224,0,2,L312
L312:
L$15:
.stabn 68,0,83,L313
L313:
LDA _Check_count,0,0
add a,@1
STA _Check_count,0,0
.stabn 68,0,84,L314
L314:
bc _TM1SF,0
.stabn 68,0,85,L315
L315:
.stabn 68,0,87,L316
L316:
.stabn 68,0,88,L317
L317:
.stabn 224,0,1,L318
L318:
L$2:
L$3:
.stabn 68,0,89,L319
L319:
.stabn 224,0,0,L320
L320:
L$1:
reti
.STACK ALLint_bp,local,0
public _INT_interrupt_l
public INT_interrupt_l_bp
.stabs "INT_interrupt_l:F15",36,0,0,_INT_interrupt_l
.section ".S1",C_CODE
.SYMDEF ".S1" LOWINT:0,2
_INT_interrupt_l:
.SYMDEF "_INT_interrupt_l" LOWINT:0,2
.stabn 192,0,0,L322
L322:
.stabn 68,0,92,L323
L323:
.stabn 68,0,93,L324
L324:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(93):"
MOV A,0x2
.stabn 68,0,93,L325
L325:
.stabn 68,0,94,L326
L326:
.stabn 224,0,0,L327
L327:
L$321:
reti
.STACK INT_interrupt_l_bp,local,0
public _TM1_interrupt_l
public TM1_interrupt_l_bp
.stabs "TM1_interrupt_l:F15",36,0,0,_TM1_interrupt_l
.section ".S2",C_CODE
.SYMDEF ".S2" LOWINT:10,60
_TM1_interrupt_l:
.SYMDEF "_TM1_interrupt_l" LOWINT:10,60
.stabn 192,0,0,L329
L329:
.stabn 68,0,96,L330
L330:
.stabn 68,0,97,L331
L331:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(97):"
MOV A,0x2
.stabn 68,0,97,L332
L332:
.stabn 68,0,98,L333
L333:
.stabn 224,0,0,L334
L334:
L$328:
reti
.STACK TM1_interrupt_l_bp,local,0
public _UART_interrupt_l
public UART_interrupt_l_bp
.stabs "UART_interrupt_l:F15",36,0,0,_UART_interrupt_l
.section ".S3",C_CODE
.SYMDEF ".S3" LOWINT:7,48
_UART_interrupt_l:
.SYMDEF "_UART_interrupt_l" LOWINT:7,48
.stabn 192,0,0,L336
L336:
.stabn 68,0,100,L337
L337:
.stabn 68,0,101,L338
L338:
.cfile "D:\YKS4509N-A96F928N V1.2\Interrupt.c(101):"
MOV A,0x2
.stabn 68,0,101,L339
L339:
.stabn 68,0,102,L340
L340:
.stabn 224,0,0,L341
L341:
L$335:
reti
.STACK UART_interrupt_l_bp,local,0
extrn _r_code_bitcoun
.section ".code"
.section ".bss"
public _count
.align 1
_count:
.SYMDEF "_count" LEN:1
ds 1
.stabs "count:G10",32,0,0,_count
extrn _IntVecIdx
.section ".bss"
extrn _flag_rec_err
.section ".bss"
extrn _flag_send_data
.section ".bss"
extrn _mandatory_net
.section ".bss"
public _Bus_task
.align 1
_Bus_task:
.SYMDEF "_Bus_task" BIT,LEN:1
ds 1
.stabs "Bus_task:G16",32,0,0,_Bus_task@BIT
extrn _Delay_nms
.section ".bss"
extrn _Rece_info
.section ".bss"
extrn _The_Bus
.section ".bss"
public _reg_acc
.align 1
_reg_acc:
.SYMDEF "_reg_acc" LEN:1
ds 1
.stabs "reg_acc:G10",32,0,0,_reg_acc
extrn _Check_count
.section ".bss"
public _rece_count
.align 1
_rece_count:
.SYMDEF "_rece_count" LEN:1
ds 1
.stabs "rece_count:G10",32,0,0,_rece_count
public _rece_data
.align 1
_rece_data:
.SYMDEF "_rece_data" LEN:15
ds 15
.stabs ":t17=ar1;0;14;10",128,0,0,0
.stabs "rece_data:G17",32,0,0,_rece_data
extrn _XS_count
.section ".bss"
extrn _KEY_INT_Det
.section ".bss"
.align 1
_LOCKEN:
.SYMDEF "_LOCKEN" REG:2,BIT:7,72,LEN:1
ds 1
.stabs "LOCKEN:S16",40,0,0,_LOCKEN
.align 1
_TLED0:
.SYMDEF "_TLED0" REG:2,BIT:0,54,LEN:1
ds 1
.stabs "TLED0:S16",40,0,0,_TLED0
.align 1
_TLED1:
.SYMDEF "_TLED1" REG:2,BIT:1,54,LEN:1
ds 1
.stabs "TLED1:S16",40,0,0,_TLED1
.align 1
_TLED2:
.SYMDEF "_TLED2" REG:2,BIT:2,54,LEN:1
ds 1
.stabs "TLED2:S16",40,0,0,_TLED2
.align 1
_TLED3:
.SYMDEF "_TLED3" REG:2,BIT:3,54,LEN:1
ds 1
.stabs "TLED3:S16",40,0,0,_TLED3
.align 1
_TLED4:
.SYMDEF "_TLED4" REG:2,BIT:4,54,LEN:1
ds 1
.stabs "TLED4:S16",40,0,0,_TLED4
.align 1
_TLED5:
.SYMDEF "_TLED5" REG:2,BIT:5,54,LEN:1
ds 1
.stabs "TLED5:S16",40,0,0,_TLED5
.align 1
_TLED6:
.SYMDEF "_TLED6" REG:2,BIT:6,54,LEN:1
ds 1
.stabs "TLED6:S16",40,0,0,_TLED6
.align 1
_TLED7:
.SYMDEF "_TLED7" REG:2,BIT:7,54,LEN:1
ds 1
.stabs "TLED7:S16",40,0,0,_TLED7
.align 1
_VR_HOLD_SEL:
.SYMDEF "_VR_HOLD_SEL" REG:2,BIT:0,62,LEN:1
ds 1
.stabs "VR_HOLD_SEL:S16",40,0,0,_VR_HOLD_SEL
.align 1
_IGCAP0:
.SYMDEF "_IGCAP0" REG:2,BIT:1,62,LEN:1
ds 1
.stabs "IGCAP0:S16",40,0,0,_IGCAP0
.align 1
_IGCAP1:
.SYMDEF "_IGCAP1" REG:2,BIT:2,62,LEN:1
ds 1
.stabs "IGCAP1:S16",40,0,0,_IGCAP1
.align 1
_IGCAP2:
.SYMDEF "_IGCAP2" REG:2,BIT:3,62,LEN:1
ds 1
.stabs "IGCAP2:S16",40,0,0,_IGCAP2
.align 1
_PVRS:
.SYMDEF "_PVRS" REG:2,BIT:4,62,LEN:1
ds 1
.stabs "PVRS:S16",40,0,0,_PVRS
.align 1
_SUBVS:
.SYMDEF "_SUBVS" REG:2,BIT:6,62,LEN:1
ds 1
.stabs "SUBVS:S16",40,0,0,_SUBVS
.align 1
_IGVS:
.SYMDEF "_IGVS" REG:2,BIT:7,62,LEN:1
ds 1
.stabs "IGVS:S16",40,0,0,_IGVS
.align 1
_IRCPDS:
.SYMDEF "_IRCPDS" REG:2,BIT:0,53,LEN:1
ds 1
.stabs "IRCPDS:S16",40,0,0,_IRCPDS
.align 1
_IGCRUN:
.SYMDEF "_IGCRUN" REG:2,BIT:0,34,LEN:1
ds 1
.stabs "IGCRUN:S16",40,0,0,_IGCRUN
.align 1
_IGOF:
.SYMDEF "_IGOF" REG:2,BIT:1,34,LEN:1
ds 1
.stabs "IGOF:S16",40,0,0,_IGOF
.align 1
_IGSM:
.SYMDEF "_IGSM" REG:2,BIT:0,33,LEN:1
ds 1
.stabs "IGSM:S16",40,0,0,_IGSM
.align 1
_IGM:
.SYMDEF "_IGM" REG:2,BIT:4,33,LEN:1
ds 1
.stabs "IGM:S16",40,0,0,_IGM
.align 1
_IGTIREN:
.SYMDEF "_IGTIREN" REG:2,BIT:6,33,LEN:1
ds 1
.stabs "IGTIREN:S16",40,0,0,_IGTIREN
.align 1
_IGTES:
.SYMDEF "_IGTES" REG:2,BIT:7,33,LEN:1
ds 1
.stabs "IGTES:S16",40,0,0,_IGTES
.align 1
_IRS:
.SYMDEF "_IRS" REG:2,BIT:7,32,LEN:1
ds 1
.stabs "IRS:S16",40,0,0,_IRS
.align 1
_GAIN0:
.SYMDEF "_GAIN0" REG:2,BIT:0,31,LEN:1
ds 1
.stabs "GAIN0:S16",40,0,0,_GAIN0
.align 1
_GAIN1:
.SYMDEF "_GAIN1" REG:2,BIT:1,31,LEN:1
ds 1
.stabs "GAIN1:S16",40,0,0,_GAIN1
.align 1
_TRCAPSEL:
.SYMDEF "_TRCAPSEL" REG:2,BIT:3,31,LEN:1
ds 1
.stabs "TRCAPSEL:S16",40,0,0,_TRCAPSEL
.align 1
_IGSTEN:
.SYMDEF "_IGSTEN" REG:2,BIT:5,31,LEN:1
ds 1
.stabs "IGSTEN:S16",40,0,0,_IGSTEN
.align 1
_IGRUN:
.SYMDEF "_IGRUN" REG:2,BIT:6,31,LEN:1
ds 1
.stabs "IGRUN:S16",40,0,0,_IGRUN
.align 1
_IGPD:
.SYMDEF "_IGPD" REG:2,BIT:7,31,LEN:1
ds 1
.stabs "IGPD:S16",40,0,0,_IGPD
.align 1
_BDPD:
.SYMDEF "_BDPD" REG:2,BIT:7,29,LEN:1
ds 1
.stabs "BDPD:S16",40,0,0,_BDPD
.align 1
_VBSTSC0:
.SYMDEF "_VBSTSC0" REG:2,BIT:0,28,LEN:1
ds 1
.stabs "VBSTSC0:S16",40,0,0,_VBSTSC0
.align 1
_VBSTSC1:
.SYMDEF "_VBSTSC1" REG:2,BIT:1,28,LEN:1
ds 1
.stabs "VBSTSC1:S16",40,0,0,_VBSTSC1
.align 1
_VBSTSC2:
.SYMDEF "_VBSTSC2" REG:2,BIT:2,28,LEN:1
ds 1
.stabs "VBSTSC2:S16",40,0,0,_VBSTSC2
.align 1
_BSTDS0:
.SYMDEF "_BSTDS0" REG:2,BIT:3,28,LEN:1
ds 1
.stabs "BSTDS0:S16",40,0,0,_BSTDS0
.align 1
_BSTDS1:
.SYMDEF "_BSTDS1" REG:2,BIT:4,28,LEN:1
ds 1
.stabs "BSTDS1:S16",40,0,0,_BSTDS1
.align 1
_BSTDS2:
.SYMDEF "_BSTDS2" REG:2,BIT:5,28,LEN:1
ds 1
.stabs "BSTDS2:S16",40,0,0,_BSTDS2
.align 1
_BSTCF:
.SYMDEF "_BSTCF" REG:2,BIT:6,28,LEN:1
ds 1
.stabs "BSTCF:S16",40,0,0,_BSTCF
.align 1
_BSTEN:
.SYMDEF "_BSTEN" REG:2,BIT:7,28,LEN:1
ds 1
.stabs "BSTEN:S16",40,0,0,_BSTEN
.align 1
_TM1IE:
.SYMDEF "_TM1IE" REG:2,BIT:0,27,LEN:1
ds 1
.stabs "TM1IE:S16",40,0,0,_TM1IE
.align 1
_TM2IE:
.SYMDEF "_TM2IE" REG:2,BIT:1,27,LEN:1
ds 1
.stabs "TM2IE:S16",40,0,0,_TM2IE
.align 1
_BSTIE:
.SYMDEF "_BSTIE" REG:2,BIT:3,27,LEN:1
ds 1
.stabs "BSTIE:S16",40,0,0,_BSTIE
.align 1
_IGIE:
.SYMDEF "_IGIE" REG:2,BIT:4,27,LEN:1
ds 1
.stabs "IGIE:S16",40,0,0,_IGIE
.align 1
_IGSG:
.SYMDEF "_IGSG" REG:2,BIT:4,26,LEN:1
ds 1
.stabs "IGSG:S16",40,0,0,_IGSG
.align 1
_IGDBS0:
.SYMDEF "_IGDBS0" REG:2,BIT:5,26,LEN:1
ds 1
.stabs "IGDBS0:S16",40,0,0,_IGDBS0
.align 1
_IGDBS1:
.SYMDEF "_IGDBS1" REG:2,BIT:6,26,LEN:1
ds 1
.stabs "IGDBS1:S16",40,0,0,_IGDBS1
.align 1
_ADCTS:
.SYMDEF "_ADCTS" REG:2,BIT:7,26,LEN:1
ds 1
.stabs "ADCTS:S16",40,0,0,_ADCTS
.align 1
_IR2EN:
.SYMDEF "_IR2EN" REG:2,BIT:7,22,LEN:1
ds 1
.stabs "IR2EN:S16",40,0,0,_IR2EN
.align 1
_IR1EN:
.SYMDEF "_IR1EN" REG:2,BIT:7,21,LEN:1
ds 1
.stabs "IR1EN:S16",40,0,0,_IR1EN
.align 1
_TM1SF:
.SYMDEF "_TM1SF" REG:2,BIT:0,20,LEN:1
ds 1
.stabs "TM1SF:S16",40,0,0,_TM1SF
.align 1
_TM2SF:
.SYMDEF "_TM2SF" REG:2,BIT:1,20,LEN:1
ds 1
.stabs "TM2SF:S16",40,0,0,_TM2SF
.align 1
_BSTSF:
.SYMDEF "_BSTSF" REG:2,BIT:3,20,LEN:1
ds 1
.stabs "BSTSF:S16",40,0,0,_BSTSF
.align 1
_IGSF:
.SYMDEF "_IGSF" REG:2,BIT:4,20,LEN:1
ds 1
.stabs "IGSF:S16",40,0,0,_IGSF
.align 1
_IGWE:
.SYMDEF "_IGWE" REG:2,BIT:0,18,LEN:1
ds 1
.stabs "IGWE:S16",40,0,0,_IGWE
.align 1
_BSTWE:
.SYMDEF "_BSTWE" REG:2,BIT:1,18,LEN:1
ds 1
.stabs "BSTWE:S16",40,0,0,_BSTWE
.align 1
_TM2CK0:
.SYMDEF "_TM2CK0" REG:2,BIT:0,12,LEN:1
ds 1
.stabs "TM2CK0:S16",40,0,0,_TM2CK0
.align 1
_TM2CK1:
.SYMDEF "_TM2CK1" REG:2,BIT:1,12,LEN:1
ds 1
.stabs "TM2CK1:S16",40,0,0,_TM2CK1
.align 1
_TM2CK2:
.SYMDEF "_TM2CK2" REG:2,BIT:2,12,LEN:1
ds 1
.stabs "TM2CK2:S16",40,0,0,_TM2CK2
.align 1
_TM2CK3:
.SYMDEF "_TM2CK3" REG:2,BIT:3,12,LEN:1
ds 1
.stabs "TM2CK3:S16",40,0,0,_TM2CK3
.align 1
_TM2SS0:
.SYMDEF "_TM2SS0" REG:2,BIT:4,12,LEN:1
ds 1
.stabs "TM2SS0:S16",40,0,0,_TM2SS0
.align 1
_TM2M0:
.SYMDEF "_TM2M0" REG:2,BIT:5,12,LEN:1
ds 1
.stabs "TM2M0:S16",40,0,0,_TM2M0
.align 1
_TM2M1:
.SYMDEF "_TM2M1" REG:2,BIT:6,12,LEN:1
ds 1
.stabs "TM2M1:S16",40,0,0,_TM2M1
.align 1
_TM2M2:
.SYMDEF "_TM2M2" REG:2,BIT:7,12,LEN:1
ds 1
.stabs "TM2M2:S16",40,0,0,_TM2M2
.align 1
_TM2IS0:
.SYMDEF "_TM2IS0" REG:2,BIT:0,11,LEN:1
ds 1
.stabs "TM2IS0:S16",40,0,0,_TM2IS0
.align 1
_TM2IS1:
.SYMDEF "_TM2IS1" REG:2,BIT:1,11,LEN:1
ds 1
.stabs "TM2IS1:S16",40,0,0,_TM2IS1
.align 1
_TM2MOS:
.SYMDEF "_TM2MOS" REG:2,BIT:2,11,LEN:1
ds 1
.stabs "TM2MOS:S16",40,0,0,_TM2MOS
.align 1
_TM2FF:
.SYMDEF "_TM2FF" REG:2,BIT:3,11,LEN:1
ds 1
.stabs "TM2FF:S16",40,0,0,_TM2FF
.align 1
_TM2SS1:
.SYMDEF "_TM2SS1" REG:2,BIT:5,11,LEN:1
ds 1
.stabs "TM2SS1:S16",40,0,0,_TM2SS1
.align 1
_TM2RC:
.SYMDEF "_TM2RC" REG:2,BIT:6,11,LEN:1
ds 1
.stabs "TM2RC:S16",40,0,0,_TM2RC
.align 1
_TM2S:
.SYMDEF "_TM2S" REG:2,BIT:7,11,LEN:1
ds 1
.stabs "TM2S:S16",40,0,0,_TM2S
.align 1
_TM1CK0:
.SYMDEF "_TM1CK0" REG:2,BIT:0,6,LEN:1
ds 1
.stabs "TM1CK0:S16",40,0,0,_TM1CK0
.align 1
_TM1CK1:
.SYMDEF "_TM1CK1" REG:2,BIT:1,6,LEN:1
ds 1
.stabs "TM1CK1:S16",40,0,0,_TM1CK1
.align 1
_TM1CK2:
.SYMDEF "_TM1CK2" REG:2,BIT:2,6,LEN:1
ds 1
.stabs "TM1CK2:S16",40,0,0,_TM1CK2
.align 1
_TM1CK3:
.SYMDEF "_TM1CK3" REG:2,BIT:3,6,LEN:1
ds 1
.stabs "TM1CK3:S16",40,0,0,_TM1CK3
.align 1
_TM1SS0:
.SYMDEF "_TM1SS0" REG:2,BIT:4,6,LEN:1
ds 1
.stabs "TM1SS0:S16",40,0,0,_TM1SS0
.align 1
_TM1M0:
.SYMDEF "_TM1M0" REG:2,BIT:5,6,LEN:1
ds 1
.stabs "TM1M0:S16",40,0,0,_TM1M0
.align 1
_TM1MOS:
.SYMDEF "_TM1MOS" REG:2,BIT:2,5,LEN:1
ds 1
.stabs "TM1MOS:S16",40,0,0,_TM1MOS
.align 1
_TM1SS1:
.SYMDEF "_TM1SS1" REG:2,BIT:5,5,LEN:1
ds 1
.stabs "TM1SS1:S16",40,0,0,_TM1SS1
.align 1
_TM1RC:
.SYMDEF "_TM1RC" REG:2,BIT:6,5,LEN:1
ds 1
.stabs "TM1RC:S16",40,0,0,_TM1RC
.align 1
_TM1S:
.SYMDEF "_TM1S" REG:2,BIT:7,5,LEN:1
ds 1
.stabs "TM1S:S16",40,0,0,_TM1S
.align 1
_IAPEN:
.SYMDEF "_IAPEN" REG:1,BIT:0,77,LEN:1
ds 1
.stabs "IAPEN:S16",40,0,0,_IAPEN
.align 1
_STOV:
.SYMDEF "_STOV" REG:1,BIT:7,71,LEN:1
ds 1
.stabs "STOV:S16",40,0,0,_STOV
.align 1
_RDS:
.SYMDEF "_RDS" REG:1,BIT:6,70,LEN:1
ds 1
.stabs "RDS:S16",40,0,0,_RDS
.align 1
_HLB:
.SYMDEF "_HLB" REG:1,BIT:7,70,LEN:1
ds 1
.stabs "HLB:S16",40,0,0,_HLB
.align 1
_EEPC:
.SYMDEF "_EEPC" REG:1,BIT:5,65,LEN:1
ds 1
.stabs "EEPC:S16",40,0,0,_EEPC
.align 1
_EEDF:
.SYMDEF "_EEDF" REG:1,BIT:6,65,LEN:1
ds 1
.stabs "EEDF:S16",40,0,0,_EEDF
.align 1
_EEWE:
.SYMDEF "_EEWE" REG:1,BIT:7,65,LEN:1
ds 1
.stabs "EEWE:S16",40,0,0,_EEWE
.align 1
_WD:
.SYMDEF "_WD" REG:1,BIT:0,64,LEN:1
ds 1
.stabs "WD:S16",40,0,0,_WD
.align 1
_RD:
.SYMDEF "_RD" REG:1,BIT:1,64,LEN:1
ds 1
.stabs "RD:S16",40,0,0,_RD
.align 1
_URSS:
.SYMDEF "_URSS" REG:1,BIT:0,55,LEN:1
ds 1
.stabs "URSS:S16",40,0,0,_URSS
.align 1
_UARTOPT0:
.SYMDEF "_UARTOPT0" REG:1,BIT:1,55,LEN:1
ds 1
.stabs "UARTOPT0:S16",40,0,0,_UARTOPT0
.align 1
_UARTOPT1:
.SYMDEF "_UARTOPT1" REG:1,BIT:2,55,LEN:1
ds 1
.stabs "UARTOPT1:S16",40,0,0,_UARTOPT1
.align 1
_UARTSP0:
.SYMDEF "_UARTSP0" REG:1,BIT:3,55,LEN:1
ds 1
.stabs "UARTSP0:S16",40,0,0,_UARTSP0
.align 1
_UARTSP1:
.SYMDEF "_UARTSP1" REG:1,BIT:4,55,LEN:1
ds 1
.stabs "UARTSP1:S16",40,0,0,_UARTSP1
.align 1
_URRD8:
.SYMDEF "_URRD8" REG:1,BIT:7,55,LEN:1
ds 1
.stabs "URRD8:S16",40,0,0,_URRD8
.align 1
_RXE:
.SYMDEF "_RXE" REG:1,BIT:0,52,LEN:1
ds 1
.stabs "RXE:S16",40,0,0,_RXE
.align 1
_URBF:
.SYMDEF "_URBF" REG:1,BIT:1,52,LEN:1
ds 1
.stabs "URBF:S16",40,0,0,_URBF
.align 1
_FMERR:
.SYMDEF "_FMERR" REG:1,BIT:2,52,LEN:1
ds 1
.stabs "FMERR:S16",40,0,0,_FMERR
.align 1
_OVERR:
.SYMDEF "_OVERR" REG:1,BIT:3,52,LEN:1
ds 1
.stabs "OVERR:S16",40,0,0,_OVERR
.align 1
_PRERR:
.SYMDEF "_PRERR" REG:1,BIT:4,52,LEN:1
ds 1
.stabs "PRERR:S16",40,0,0,_PRERR
.align 1
_PRE:
.SYMDEF "_PRE" REG:1,BIT:5,52,LEN:1
ds 1
.stabs "PRE:S16",40,0,0,_PRE
.align 1
_EVEN:
.SYMDEF "_EVEN" REG:1,BIT:6,52,LEN:1
ds 1
.stabs "EVEN:S16",40,0,0,_EVEN
.align 1
_URTD8:
.SYMDEF "_URTD8" REG:1,BIT:7,52,LEN:1
ds 1
.stabs "URTD8:S16",40,0,0,_URTD8
.align 1
_TXE:
.SYMDEF "_TXE" REG:1,BIT:0,51,LEN:1
ds 1
.stabs "TXE:S16",40,0,0,_TXE
.align 1
_UTBF:
.SYMDEF "_UTBF" REG:1,BIT:1,51,LEN:1
ds 1
.stabs "UTBF:S16",40,0,0,_UTBF
.align 1
_BRATE0:
.SYMDEF "_BRATE0" REG:1,BIT:2,51,LEN:1
ds 1
.stabs "BRATE0:S16",40,0,0,_BRATE0
.align 1
_BRATE1:
.SYMDEF "_BRATE1" REG:1,BIT:3,51,LEN:1
ds 1
.stabs "BRATE1:S16",40,0,0,_BRATE1
.align 1
_BRATE2:
.SYMDEF "_BRATE2" REG:1,BIT:4,51,LEN:1
ds 1
.stabs "BRATE2:S16",40,0,0,_BRATE2
.align 1
_UMOCE0:
.SYMDEF "_UMOCE0" REG:1,BIT:5,51,LEN:1
ds 1
.stabs "UMOCE0:S16",40,0,0,_UMOCE0
.align 1
_UMODE1:
.SYMDEF "_UMODE1" REG:1,BIT:6,51,LEN:1
ds 1
.stabs "UMODE1:S16",40,0,0,_UMODE1
.align 1
_UINVEN:
.SYMDEF "_UINVEN" REG:1,BIT:7,51,LEN:1
ds 1
.stabs "UINVEN:S16",40,0,0,_UINVEN
.align 1
_OD60:
.SYMDEF "_OD60" REG:1,BIT:0,18,LEN:1
ds 1
.stabs "OD60:S16",40,0,0,_OD60
.align 1
_OD61:
.SYMDEF "_OD61" REG:1,BIT:1,18,LEN:1
ds 1
.stabs "OD61:S16",40,0,0,_OD61
.align 1
_OD62:
.SYMDEF "_OD62" REG:1,BIT:2,18,LEN:1
ds 1
.stabs "OD62:S16",40,0,0,_OD62
.align 1
_OD50:
.SYMDEF "_OD50" REG:1,BIT:0,17,LEN:1
ds 1
.stabs "OD50:S16",40,0,0,_OD50
.align 1
_OD51:
.SYMDEF "_OD51" REG:1,BIT:1,17,LEN:1
ds 1
.stabs "OD51:S16",40,0,0,_OD51
.align 1
_OD52:
.SYMDEF "_OD52" REG:1,BIT:2,17,LEN:1
ds 1
.stabs "OD52:S16",40,0,0,_OD52
.align 1
_OD53:
.SYMDEF "_OD53" REG:1,BIT:3,17,LEN:1
ds 1
.stabs "OD53:S16",40,0,0,_OD53
.align 1
_OD54:
.SYMDEF "_OD54" REG:1,BIT:4,17,LEN:1
ds 1
.stabs "OD54:S16",40,0,0,_OD54
.align 1
_OD55:
.SYMDEF "_OD55" REG:1,BIT:5,17,LEN:1
ds 1
.stabs "OD55:S16",40,0,0,_OD55
.align 1
_OD56:
.SYMDEF "_OD56" REG:1,BIT:6,17,LEN:1
ds 1
.stabs "OD56:S16",40,0,0,_OD56
.align 1
_OD57:
.SYMDEF "_OD57" REG:1,BIT:7,17,LEN:1
ds 1
.stabs "OD57:S16",40,0,0,_OD57
.align 1
_H60:
.SYMDEF "_H60" REG:1,BIT:0,15,LEN:1
ds 1
.stabs "H60:S16",40,0,0,_H60
.align 1
_H61:
.SYMDEF "_H61" REG:1,BIT:1,15,LEN:1
ds 1
.stabs "H61:S16",40,0,0,_H61
.align 1
_H62:
.SYMDEF "_H62" REG:1,BIT:2,15,LEN:1
ds 1
.stabs "H62:S16",40,0,0,_H62
.align 1
_H50:
.SYMDEF "_H50" REG:1,BIT:0,14,LEN:1
ds 1
.stabs "H50:S16",40,0,0,_H50
.align 1
_H51:
.SYMDEF "_H51" REG:1,BIT:1,14,LEN:1
ds 1
.stabs "H51:S16",40,0,0,_H51
.align 1
_H52:
.SYMDEF "_H52" REG:1,BIT:2,14,LEN:1
ds 1
.stabs "H52:S16",40,0,0,_H52
.align 1
_H53:
.SYMDEF "_H53" REG:1,BIT:3,14,LEN:1
ds 1
.stabs "H53:S16",40,0,0,_H53
.align 1
_H54:
.SYMDEF "_H54" REG:1,BIT:4,14,LEN:1
ds 1
.stabs "H54:S16",40,0,0,_H54
.align 1
_H55:
.SYMDEF "_H55" REG:1,BIT:5,14,LEN:1
ds 1
.stabs "H55:S16",40,0,0,_H55
.align 1
_H56:
.SYMDEF "_H56" REG:1,BIT:6,14,LEN:1
ds 1
.stabs "H56:S16",40,0,0,_H56
.align 1
_H57:
.SYMDEF "_H57" REG:1,BIT:7,14,LEN:1
ds 1
.stabs "H57:S16",40,0,0,_H57
.align 1
_PL60:
.SYMDEF "_PL60" REG:1,BIT:0,12,LEN:1
ds 1
.stabs "PL60:S16",40,0,0,_PL60
.align 1
_PL61:
.SYMDEF "_PL61" REG:1,BIT:1,12,LEN:1
ds 1
.stabs "PL61:S16",40,0,0,_PL61
.align 1
_PL62:
.SYMDEF "_PL62" REG:1,BIT:2,12,LEN:1
ds 1
.stabs "PL62:S16",40,0,0,_PL62
.align 1
_PL50:
.SYMDEF "_PL50" REG:1,BIT:0,11,LEN:1
ds 1
.stabs "PL50:S16",40,0,0,_PL50
.align 1
_PL51:
.SYMDEF "_PL51" REG:1,BIT:1,11,LEN:1
ds 1
.stabs "PL51:S16",40,0,0,_PL51
.align 1
_PL52:
.SYMDEF "_PL52" REG:1,BIT:2,11,LEN:1
ds 1
.stabs "PL52:S16",40,0,0,_PL52
.align 1
_PL53:
.SYMDEF "_PL53" REG:1,BIT:3,11,LEN:1
ds 1
.stabs "PL53:S16",40,0,0,_PL53
.align 1
_PL54:
.SYMDEF "_PL54" REG:1,BIT:4,11,LEN:1
ds 1
.stabs "PL54:S16",40,0,0,_PL54
.align 1
_PL55:
.SYMDEF "_PL55" REG:1,BIT:5,11,LEN:1
ds 1
.stabs "PL55:S16",40,0,0,_PL55
.align 1
_PL56:
.SYMDEF "_PL56" REG:1,BIT:6,11,LEN:1
ds 1
.stabs "PL56:S16",40,0,0,_PL56
.align 1
_PL57:
.SYMDEF "_PL57" REG:1,BIT:7,11,LEN:1
ds 1
.stabs "PL57:S16",40,0,0,_PL57
.align 1
_PH60:
.SYMDEF "_PH60" REG:1,BIT:0,9,LEN:1
ds 1
.stabs "PH60:S16",40,0,0,_PH60
.align 1
_PH61:
.SYMDEF "_PH61" REG:1,BIT:1,9,LEN:1
ds 1
.stabs "PH61:S16",40,0,0,_PH61
.align 1
_PH62:
.SYMDEF "_PH62" REG:1,BIT:2,9,LEN:1
ds 1
.stabs "PH62:S16",40,0,0,_PH62
.align 1
_PH50:
.SYMDEF "_PH50" REG:1,BIT:0,8,LEN:1
ds 1
.stabs "PH50:S16",40,0,0,_PH50
.align 1
_PH51:
.SYMDEF "_PH51" REG:1,BIT:1,8,LEN:1
ds 1
.stabs "PH51:S16",40,0,0,_PH51
.align 1
_PH52:
.SYMDEF "_PH52" REG:1,BIT:2,8,LEN:1
ds 1
.stabs "PH52:S16",40,0,0,_PH52
.align 1
_PH53:
.SYMDEF "_PH53" REG:1,BIT:3,8,LEN:1
ds 1
.stabs "PH53:S16",40,0,0,_PH53
.align 1
_PH54:
.SYMDEF "_PH54" REG:1,BIT:4,8,LEN:1
ds 1
.stabs "PH54:S16",40,0,0,_PH54
.align 1
_PH55:
.SYMDEF "_PH55" REG:1,BIT:5,8,LEN:1
ds 1
.stabs "PH55:S16",40,0,0,_PH55
.align 1
_PH56:
.SYMDEF "_PH56" REG:1,BIT:6,8,LEN:1
ds 1
.stabs "PH56:S16",40,0,0,_PH56
.align 1
_PH57:
.SYMDEF "_PH57" REG:1,BIT:7,8,LEN:1
ds 1
.stabs "PH57:S16",40,0,0,_PH57
.align 1
_ADE0:
.SYMDEF "_ADE0" REG:0,BIT:0,65,LEN:1
ds 1
.stabs "ADE0:S16",40,0,0,_ADE0
.align 1
_ADE1:
.SYMDEF "_ADE1" REG:0,BIT:1,65,LEN:1
ds 1
.stabs "ADE1:S16",40,0,0,_ADE1
.align 1
_ADE2:
.SYMDEF "_ADE2" REG:0,BIT:2,65,LEN:1
ds 1
.stabs "ADE2:S16",40,0,0,_ADE2
.align 1
_ADE3:
.SYMDEF "_ADE3" REG:0,BIT:3,65,LEN:1
ds 1
.stabs "ADE3:S16",40,0,0,_ADE3
.align 1
_ADE4:
.SYMDEF "_ADE4" REG:0,BIT:4,65,LEN:1
ds 1
.stabs "ADE4:S16",40,0,0,_ADE4
.align 1
_ADE5:
.SYMDEF "_ADE5" REG:0,BIT:5,65,LEN:1
ds 1
.stabs "ADE5:S16",40,0,0,_ADE5
.align 1
_ADE6:
.SYMDEF "_ADE6" REG:0,BIT:6,65,LEN:1
ds 1
.stabs "ADE6:S16",40,0,0,_ADE6
.align 1
_ADE7:
.SYMDEF "_ADE7" REG:0,BIT:7,65,LEN:1
ds 1
.stabs "ADE7:S16",40,0,0,_ADE7
.align 1
_ADIS0:
.SYMDEF "_ADIS0" REG:0,BIT:0,64,LEN:1
ds 1
.stabs "ADIS0:S16",40,0,0,_ADIS0
.align 1
_ADIS1:
.SYMDEF "_ADIS1" REG:0,BIT:1,64,LEN:1
ds 1
.stabs "ADIS1:S16",40,0,0,_ADIS1
.align 1
_ADIS2:
.SYMDEF "_ADIS2" REG:0,BIT:2,64,LEN:1
ds 1
.stabs "ADIS2:S16",40,0,0,_ADIS2
.align 1
_ADIS3:
.SYMDEF "_ADIS3" REG:0,BIT:3,64,LEN:1
ds 1
.stabs "ADIS3:S16",40,0,0,_ADIS3
.align 1
_TSLPFEN:
.SYMDEF "_TSLPFEN" REG:0,BIT:7,64,LEN:1
ds 1
.stabs "TSLPFEN:S16",40,0,0,_TSLPFEN
.align 1
_VREFP0:
.SYMDEF "_VREFP0" REG:0,BIT:0,63,LEN:1
ds 1
.stabs "VREFP0:S16",40,0,0,_VREFP0
.align 1
_VREFP1:
.SYMDEF "_VREFP1" REG:0,BIT:1,63,LEN:1
ds 1
.stabs "VREFP1:S16",40,0,0,_VREFP1
.align 1
_VPIS0:
.SYMDEF "_VPIS0" REG:0,BIT:2,63,LEN:1
ds 1
.stabs "VPIS0:S16",40,0,0,_VPIS0
.align 1
_ADCMS:
.SYMDEF "_ADCMS" REG:0,BIT:4,63,LEN:1
ds 1
.stabs "ADCMS:S16",40,0,0,_ADCMS
.align 1
_ADIM:
.SYMDEF "_ADIM" REG:0,BIT:5,63,LEN:1
ds 1
.stabs "ADIM:S16",40,0,0,_ADIM
.align 1
_ADLPFEN:
.SYMDEF "_ADLPFEN" REG:0,BIT:7,63,LEN:1
ds 1
.stabs "ADLPFEN:S16",40,0,0,_ADLPFEN
.align 1
_SHS0:
.SYMDEF "_SHS0" REG:0,BIT:0,62,LEN:1
ds 1
.stabs "SHS0:S16",40,0,0,_SHS0
.align 1
_SHS1:
.SYMDEF "_SHS1" REG:0,BIT:1,62,LEN:1
ds 1
.stabs "SHS1:S16",40,0,0,_SHS1
.align 1
_ADOM:
.SYMDEF "_ADOM" REG:0,BIT:2,62,LEN:1
ds 1
.stabs "ADOM:S16",40,0,0,_ADOM
.align 1
_ADP:
.SYMDEF "_ADP" REG:0,BIT:3,62,LEN:1
ds 1
.stabs "ADP:S16",40,0,0,_ADP
.align 1
_ADRUN:
.SYMDEF "_ADRUN" REG:0,BIT:4,62,LEN:1
ds 1
.stabs "ADRUN:S16",40,0,0,_ADRUN
.align 1
_CKR0:
.SYMDEF "_CKR0" REG:0,BIT:5,62,LEN:1
ds 1
.stabs "CKR0:S16",40,0,0,_CKR0
.align 1
_CKR1:
.SYMDEF "_CKR1" REG:0,BIT:6,62,LEN:1
ds 1
.stabs "CKR1:S16",40,0,0,_CKR1
.align 1
_CKR2:
.SYMDEF "_CKR2" REG:0,BIT:7,62,LEN:1
ds 1
.stabs "CKR2:S16",40,0,0,_CKR2
.align 1
_RBF:
.SYMDEF "_RBF" REG:0,BIT:0,55,LEN:1
ds 1
.stabs "RBF:S16",40,0,0,_RBF
.align 1
_OD4:
.SYMDEF "_OD4" REG:0,BIT:2,55,LEN:1
ds 1
.stabs "OD4:S16",40,0,0,_OD4
.align 1
_OD3:
.SYMDEF "_OD3" REG:0,BIT:3,55,LEN:1
ds 1
.stabs "OD3:S16",40,0,0,_OD3
.align 1
_TD0:
.SYMDEF "_TD0" REG:0,BIT:5,55,LEN:1
ds 1
.stabs "TD0:S16",40,0,0,_TD0
.align 1
_TD1:
.SYMDEF "_TD1" REG:0,BIT:6,55,LEN:1
ds 1
.stabs "TD1:S16",40,0,0,_TD1
.align 1
_DOPD:
.SYMDEF "_DOPD" REG:0,BIT:7,55,LEN:1
ds 1
.stabs "DOPD:S16",40,0,0,_DOPD
.align 1
_SBRS0:
.SYMDEF "_SBRS0" REG:0,BIT:0,54,LEN:1
ds 1
.stabs "SBRS0:S16",40,0,0,_SBRS0
.align 1
_SBRS1:
.SYMDEF "_SBRS1" REG:0,BIT:1,54,LEN:1
ds 1
.stabs "SBRS1:S16",40,0,0,_SBRS1
.align 1
_SBRS2:
.SYMDEF "_SBRS2" REG:0,BIT:2,54,LEN:1
ds 1
.stabs "SBRS2:S16",40,0,0,_SBRS2
.align 1
_SDOC:
.SYMDEF "_SDOC" REG:0,BIT:3,54,LEN:1
ds 1
.stabs "SDOC:S16",40,0,0,_SDOC
.align 1
_SSE:
.SYMDEF "_SSE" REG:0,BIT:4,54,LEN:1
ds 1
.stabs "SSE:S16",40,0,0,_SSE
.align 1
_SRO:
.SYMDEF "_SRO" REG:0,BIT:5,54,LEN:1
ds 1
.stabs "SRO:S16",40,0,0,_SRO
.align 1
_SPIE:
.SYMDEF "_SPIE" REG:0,BIT:6,54,LEN:1
ds 1
.stabs "SPIE:S16",40,0,0,_SPIE
.align 1
_CES:
.SYMDEF "_CES" REG:0,BIT:7,54,LEN:1
ds 1
.stabs "CES:S16",40,0,0,_CES
.align 1
_WPSR0:
.SYMDEF "_WPSR0" REG:0,BIT:0,33,LEN:1
ds 1
.stabs "WPSR0:S16",40,0,0,_WPSR0
.align 1
_WPSR1:
.SYMDEF "_WPSR1" REG:0,BIT:1,33,LEN:1
ds 1
.stabs "WPSR1:S16",40,0,0,_WPSR1
.align 1
_WPSR2:
.SYMDEF "_WPSR2" REG:0,BIT:2,33,LEN:1
ds 1
.stabs "WPSR2:S16",40,0,0,_WPSR2
.align 1
_PSWE:
.SYMDEF "_PSWE" REG:0,BIT:3,33,LEN:1
ds 1
.stabs "PSWE:S16",40,0,0,_PSWE
.align 1
_FSSF:
.SYMDEF "_FSSF" REG:0,BIT:6,33,LEN:1
ds 1
.stabs "FSSF:S16",40,0,0,_FSSF
.align 1
_WDTE:
.SYMDEF "_WDTE" REG:0,BIT:7,33,LEN:1
ds 1
.stabs "WDTE:S16",40,0,0,_WDTE
.align 1
_SHIE:
.SYMDEF "_SHIE" REG:0,BIT:7,32,LEN:1
ds 1
.stabs "SHIE:S16",40,0,0,_SHIE
.align 1
_EXIE2:
.SYMDEF "_EXIE2" REG:0,BIT:0,31,LEN:1
ds 1
.stabs "EXIE2:S16",40,0,0,_EXIE2
.align 1
_SPIIE:
.SYMDEF "_SPIIE" REG:0,BIT:3,30,LEN:1
ds 1
.stabs "SPIIE:S16",40,0,0,_SPIIE
.align 1
_P5ICIE:
.SYMDEF "_P5ICIE" REG:0,BIT:4,30,LEN:1
ds 1
.stabs "P5ICIE:S16",40,0,0,_P5ICIE
.align 1
_P6ICIE:
.SYMDEF "_P6ICIE" REG:0,BIT:5,30,LEN:1
ds 1
.stabs "P6ICIE:S16",40,0,0,_P6ICIE
.align 1
_UTIE:
.SYMDEF "_UTIE" REG:0,BIT:3,28,LEN:1
ds 1
.stabs "UTIE:S16",40,0,0,_UTIE
.align 1
_URIE:
.SYMDEF "_URIE" REG:0,BIT:4,28,LEN:1
ds 1
.stabs "URIE:S16",40,0,0,_URIE
.align 1
_UERRIE:
.SYMDEF "_UERRIE" REG:0,BIT:5,28,LEN:1
ds 1
.stabs "UERRIE:S16",40,0,0,_UERRIE
.align 1
_EXIE0:
.SYMDEF "_EXIE0" REG:0,BIT:2,27,LEN:1
ds 1
.stabs "EXIE0:S16",40,0,0,_EXIE0
.align 1
_EXIE1:
.SYMDEF "_EXIE1" REG:0,BIT:3,27,LEN:1
ds 1
.stabs "EXIE1:S16",40,0,0,_EXIE1
.align 1
_ADIE:
.SYMDEF "_ADIE" REG:0,BIT:4,27,LEN:1
ds 1
.stabs "ADIE:S16",40,0,0,_ADIE
.align 1
_SHSF:
.SYMDEF "_SHSF" REG:0,BIT:7,25,LEN:1
ds 1
.stabs "SHSF:S16",40,0,0,_SHSF
.align 1
_EXSF2:
.SYMDEF "_EXSF2" REG:0,BIT:0,24,LEN:1
ds 1
.stabs "EXSF2:S16",40,0,0,_EXSF2
.align 1
_SPISF:
.SYMDEF "_SPISF" REG:0,BIT:3,23,LEN:1
ds 1
.stabs "SPISF:S16",40,0,0,_SPISF
.align 1
_P5ICSF:
.SYMDEF "_P5ICSF" REG:0,BIT:4,23,LEN:1
ds 1
.stabs "P5ICSF:S16",40,0,0,_P5ICSF
.align 1
_P6ICSF:
.SYMDEF "_P6ICSF" REG:0,BIT:5,23,LEN:1
ds 1
.stabs "P6ICSF:S16",40,0,0,_P6ICSF
.align 1
_UTSF:
.SYMDEF "_UTSF" REG:0,BIT:3,21,LEN:1
ds 1
.stabs "UTSF:S16",40,0,0,_UTSF
.align 1
_URSF:
.SYMDEF "_URSF" REG:0,BIT:4,21,LEN:1
ds 1
.stabs "URSF:S16",40,0,0,_URSF
.align 1
_UERRSF:
.SYMDEF "_UERRSF" REG:0,BIT:5,21,LEN:1
ds 1
.stabs "UERRSF:S16",40,0,0,_UERRSF
.align 1
_EXSF0:
.SYMDEF "_EXSF0" REG:0,BIT:2,20,LEN:1
ds 1
.stabs "EXSF0:S16",40,0,0,_EXSF0
.align 1
_EXSF1:
.SYMDEF "_EXSF1" REG:0,BIT:3,20,LEN:1
ds 1
.stabs "EXSF1:S16",40,0,0,_EXSF1
.align 1
_ADSF:
.SYMDEF "_ADSF" REG:0,BIT:4,20,LEN:1
ds 1
.stabs "ADSF:S16",40,0,0,_ADSF
.align 1
_INT2WK:
.SYMDEF "_INT2WK" REG:0,BIT:0,18,LEN:1
ds 1
.stabs "INT2WK:S16",40,0,0,_INT2WK
.align 1
_ICWKP5:
.SYMDEF "_ICWKP5" REG:0,BIT:4,18,LEN:1
ds 1
.stabs "ICWKP5:S16",40,0,0,_ICWKP5
.align 1
_ICWKP6:
.SYMDEF "_ICWKP6" REG:0,BIT:5,18,LEN:1
ds 1
.stabs "ICWKP6:S16",40,0,0,_ICWKP6
.align 1
_SPIWK:
.SYMDEF "_SPIWK" REG:0,BIT:3,17,LEN:1
ds 1
.stabs "SPIWK:S16",40,0,0,_SPIWK
.align 1
_URWK:
.SYMDEF "_URWK" REG:0,BIT:4,17,LEN:1
ds 1
.stabs "URWK:S16",40,0,0,_URWK
.align 1
_INT0WK:
.SYMDEF "_INT0WK" REG:0,BIT:2,16,LEN:1
ds 1
.stabs "INT0WK:S16",40,0,0,_INT0WK
.align 1
_INT1WK:
.SYMDEF "_INT1WK" REG:0,BIT:3,16,LEN:1
ds 1
.stabs "INT1WK:S16",40,0,0,_INT1WK
.align 1
_ADWK:
.SYMDEF "_ADWK" REG:0,BIT:4,16,LEN:1
ds 1
.stabs "ADWK:S16",40,0,0,_ADWK
.align 1
_EIES0:
.SYMDEF "_EIES0" REG:0,BIT:2,15,LEN:1
ds 1
.stabs "EIES0:S16",40,0,0,_EIES0
.align 1
_EIES1:
.SYMDEF "_EIES1" REG:0,BIT:3,15,LEN:1
ds 1
.stabs "EIES1:S16",40,0,0,_EIES1
.align 1
_EIES2:
.SYMDEF "_EIES2" REG:0,BIT:4,15,LEN:1
ds 1
.stabs "EIES2:S16",40,0,0,_EIES2
.align 1
_RCM0:
.SYMDEF "_RCM0" REG:0,BIT:0,14,LEN:1
ds 1
.stabs "RCM0:S16",40,0,0,_RCM0
.align 1
_RCM1:
.SYMDEF "_RCM1" REG:0,BIT:1,14,LEN:1
ds 1
.stabs "RCM1:S16",40,0,0,_RCM1
.align 1
_FMSF:
.SYMDEF "_FMSF" REG:0,BIT:3,14,LEN:1
ds 1
.stabs "FMSF:S16",40,0,0,_FMSF
.align 1
_IDLE:
.SYMDEF "_IDLE" REG:0,BIT:6,14,LEN:1
ds 1
.stabs "IDLE:S16",40,0,0,_IDLE
.align 1
_CPUS:
.SYMDEF "_CPUS" REG:0,BIT:7,14,LEN:1
ds 1
.stabs "CPUS:S16",40,0,0,_CPUS
.align 1
_P60CR:
.SYMDEF "_P60CR" REG:0,BIT:0,12,LEN:1
ds 1
.stabs "P60CR:S16",40,0,0,_P60CR
.align 1
_P61CR:
.SYMDEF "_P61CR" REG:0,BIT:1,12,LEN:1
ds 1
.stabs "P61CR:S16",40,0,0,_P61CR
.align 1
_P62CR:
.SYMDEF "_P62CR" REG:0,BIT:2,12,LEN:1
ds 1
.stabs "P62CR:S16",40,0,0,_P62CR
.align 1
_IOCR60:
.SYMDEF "_IOCR60" REG:0,BIT:0,12,LEN:1
ds 1
.stabs "IOCR60:S16",40,0,0,_IOCR60
.align 1
_IOCR61:
.SYMDEF "_IOCR61" REG:0,BIT:1,12,LEN:1
ds 1
.stabs "IOCR61:S16",40,0,0,_IOCR61
.align 1
_IOCR62:
.SYMDEF "_IOCR62" REG:0,BIT:2,12,LEN:1
ds 1
.stabs "IOCR62:S16",40,0,0,_IOCR62
.align 1
_P50CR:
.SYMDEF "_P50CR" REG:0,BIT:0,11,LEN:1
ds 1
.stabs "P50CR:S16",40,0,0,_P50CR
.align 1
_P51CR:
.SYMDEF "_P51CR" REG:0,BIT:1,11,LEN:1
ds 1
.stabs "P51CR:S16",40,0,0,_P51CR
.align 1
_P52CR:
.SYMDEF "_P52CR" REG:0,BIT:2,11,LEN:1
ds 1
.stabs "P52CR:S16",40,0,0,_P52CR
.align 1
_P53CR:
.SYMDEF "_P53CR" REG:0,BIT:3,11,LEN:1
ds 1
.stabs "P53CR:S16",40,0,0,_P53CR
.align 1
_P54CR:
.SYMDEF "_P54CR" REG:0,BIT:4,11,LEN:1
ds 1
.stabs "P54CR:S16",40,0,0,_P54CR
.align 1
_P55CR:
.SYMDEF "_P55CR" REG:0,BIT:5,11,LEN:1
ds 1
.stabs "P55CR:S16",40,0,0,_P55CR
.align 1
_P56CR:
.SYMDEF "_P56CR" REG:0,BIT:6,11,LEN:1
ds 1
.stabs "P56CR:S16",40,0,0,_P56CR
.align 1
_P57CR:
.SYMDEF "_P57CR" REG:0,BIT:7,11,LEN:1
ds 1
.stabs "P57CR:S16",40,0,0,_P57CR
.align 1
_IOCR50:
.SYMDEF "_IOCR50" REG:0,BIT:0,11,LEN:1
ds 1
.stabs "IOCR50:S16",40,0,0,_IOCR50
.align 1
_IOCR51:
.SYMDEF "_IOCR51" REG:0,BIT:1,11,LEN:1
ds 1
.stabs "IOCR51:S16",40,0,0,_IOCR51
.align 1
_IOCR52:
.SYMDEF "_IOCR52" REG:0,BIT:2,11,LEN:1
ds 1
.stabs "IOCR52:S16",40,0,0,_IOCR52
.align 1
_IOCR53:
.SYMDEF "_IOCR53" REG:0,BIT:3,11,LEN:1
ds 1
.stabs "IOCR53:S16",40,0,0,_IOCR53
.align 1
_IOCR54:
.SYMDEF "_IOCR54" REG:0,BIT:4,11,LEN:1
ds 1
.stabs "IOCR54:S16",40,0,0,_IOCR54
.align 1
_IOCR55:
.SYMDEF "_IOCR55" REG:0,BIT:5,11,LEN:1
ds 1
.stabs "IOCR55:S16",40,0,0,_IOCR55
.align 1
_IOCR56:
.SYMDEF "_IOCR56" REG:0,BIT:6,11,LEN:1
ds 1
.stabs "IOCR56:S16",40,0,0,_IOCR56
.align 1
_IOCR57:
.SYMDEF "_IOCR57" REG:0,BIT:7,11,LEN:1
ds 1
.stabs "IOCR57:S16",40,0,0,_IOCR57
.align 1
_P60:
.SYMDEF "_P60" REG:0,BIT:0,6,LEN:1
ds 1
.stabs "P60:S16",40,0,0,_P60
.align 1
_P61:
.SYMDEF "_P61" REG:0,BIT:1,6,LEN:1
ds 1
.stabs "P61:S16",40,0,0,_P61
.align 1
_P62:
.SYMDEF "_P62" REG:0,BIT:2,6,LEN:1
ds 1
.stabs "P62:S16",40,0,0,_P62
.align 1
_P50:
.SYMDEF "_P50" REG:0,BIT:0,5,LEN:1
ds 1
.stabs "P50:S16",40,0,0,_P50
.align 1
_P51:
.SYMDEF "_P51" REG:0,BIT:1,5,LEN:1
ds 1
.stabs "P51:S16",40,0,0,_P51
.align 1
_P52:
.SYMDEF "_P52" REG:0,BIT:2,5,LEN:1
ds 1
.stabs "P52:S16",40,0,0,_P52
.align 1
_P53:
.SYMDEF "_P53" REG:0,BIT:3,5,LEN:1
ds 1
.stabs "P53:S16",40,0,0,_P53
.align 1
_P54:
.SYMDEF "_P54" REG:0,BIT:4,5,LEN:1
ds 1
.stabs "P54:S16",40,0,0,_P54
.align 1
_P55:
.SYMDEF "_P55" REG:0,BIT:5,5,LEN:1
ds 1
.stabs "P55:S16",40,0,0,_P55
.align 1
_P56:
.SYMDEF "_P56" REG:0,BIT:6,5,LEN:1
ds 1
.stabs "P56:S16",40,0,0,_P56
.align 1
_P57:
.SYMDEF "_P57" REG:0,BIT:7,5,LEN:1
ds 1
.stabs "P57:S16",40,0,0,_P57
.align 1
_C:
.SYMDEF "_C" REG:0,BIT:0,3,LEN:1
ds 1
.stabs "C:S16",40,0,0,_C
.align 1
_DC:
.SYMDEF "_DC" REG:0,BIT:1,3,LEN:1
ds 1
.stabs "DC:S16",40,0,0,_DC
.align 1
_Z:
.SYMDEF "_Z" REG:0,BIT:2,3,LEN:1
ds 1
.stabs "Z:S16",40,0,0,_Z
.align 1
_P:
.SYMDEF "_P" REG:0,BIT:3,3,LEN:1
ds 1
.stabs "P:S16",40,0,0,_P
.align 1
_T:
.SYMDEF "_T" REG:0,BIT:4,3,LEN:1
ds 1
.stabs "T:S16",40,0,0,_T
.align 1
_OV:
.SYMDEF "_OV" REG:0,BIT:5,3,LEN:1
ds 1
.stabs "OV:S16",40,0,0,_OV
.align 1
_N:
.SYMDEF "_N" REG:0,BIT:6,3,LEN:1
ds 1
.stabs "N:S16",40,0,0,_N
.align 1
_INT:
.SYMDEF "_INT" REG:0,BIT:7,3,LEN:1
ds 1
.stabs "INT:S16",40,0,0,_INT
.align 1
_COBS11:
.SYMDEF "_COBS11" REG:2,68,LEN:1
ds 1
.stabs "COBS11:S14",40,0,0,_COBS11
.align 1
_COBS10:
.SYMDEF "_COBS10" REG:2,67,LEN:1
ds 1
.stabs "COBS10:S14",40,0,0,_COBS10
.align 1
_COBS9:
.SYMDEF "_COBS9" REG:2,66,LEN:1
ds 1
.stabs "COBS9:S14",40,0,0,_COBS9
.align 1
_COBS8:
.SYMDEF "_COBS8" REG:2,65,LEN:1
ds 1
.stabs "COBS8:S14",40,0,0,_COBS8
.align 1
_COBS7:
.SYMDEF "_COBS7" REG:2,64,LEN:1
ds 1
.stabs "COBS7:S14",40,0,0,_COBS7
.align 1
_COBS6:
.SYMDEF "_COBS6" REG:2,63,LEN:1
ds 1
.stabs "COBS6:S14",40,0,0,_COBS6
.align 1
_COBS5:
.SYMDEF "_COBS5" REG:2,62,LEN:1
ds 1
.stabs "COBS5:S14",40,0,0,_COBS5
.align 1
_THOLD:
.SYMDEF "_THOLD" REG:2,57,LEN:1
ds 1
.stabs "THOLD:S14",40,0,0,_THOLD
.align 1
_TCALT:
.SYMDEF "_TCALT" REG:2,56,LEN:1
ds 1
.stabs "TCALT:S14",40,0,0,_TCALT
.align 1
_TCALS:
.SYMDEF "_TCALS" REG:2,55,LEN:1
ds 1
.stabs "TCALS:S14",40,0,0,_TCALS
.align 1
_TLED:
.SYMDEF "_TLED" REG:2,54,LEN:1
ds 1
.stabs "TLED:S14",40,0,0,_TLED
.align 1
_IRCPDCR:
.SYMDEF "_IRCPDCR" REG:2,53,LEN:1
ds 1
.stabs "IRCPDCR:S14",40,0,0,_IRCPDCR
.align 1
_IGCTR2:
.SYMDEF "_IGCTR2" REG:2,41,LEN:1
ds 1
.stabs "IGCTR2:S14",40,0,0,_IGCTR2
.align 1
_IGCTR1:
.SYMDEF "_IGCTR1" REG:2,40,LEN:1
ds 1
.stabs "IGCTR1:S14",40,0,0,_IGCTR1
.align 1
_IGDCTL:
.SYMDEF "_IGDCTL" REG:2,39,LEN:1
ds 1
.stabs "IGDCTL:S14",40,0,0,_IGDCTL
.align 1
_IGDCTH:
.SYMDEF "_IGDCTH" REG:2,38,LEN:1
ds 1
.stabs "IGDCTH:S14",40,0,0,_IGDCTH
.align 1
_IGDCRL:
.SYMDEF "_IGDCRL" REG:2,37,LEN:1
ds 1
.stabs "IGDCRL:S14",40,0,0,_IGDCRL
.align 1
_IGDCRH:
.SYMDEF "_IGDCRH" REG:2,36,LEN:1
ds 1
.stabs "IGDCRH:S14",40,0,0,_IGDCRH
.align 1
_IGCCR:
.SYMDEF "_IGCCR" REG:2,34,LEN:1
ds 1
.stabs "IGCCR:S14",40,0,0,_IGCCR
.align 1
_IGCR3:
.SYMDEF "_IGCR3" REG:2,33,LEN:1
ds 1
.stabs "IGCR3:S14",40,0,0,_IGCR3
.align 1
_IGCR2:
.SYMDEF "_IGCR2" REG:2,32,LEN:1
ds 1
.stabs "IGCR2:S14",40,0,0,_IGCR2
.align 1
_IGCR1:
.SYMDEF "_IGCR1" REG:2,31,LEN:1
ds 1
.stabs "IGCR1:S14",40,0,0,_IGCR1
.align 1
_BDCR:
.SYMDEF "_BDCR" REG:2,29,LEN:1
ds 1
.stabs "BDCR:S14",40,0,0,_BDCR
.align 1
_BSTCR:
.SYMDEF "_BSTCR" REG:2,28,LEN:1
ds 1
.stabs "BSTCR:S14",40,0,0,_BSTCR
.align 1
_IMR7:
.SYMDEF "_IMR7" REG:2,27,LEN:1
ds 1
.stabs "IMR7:S14",40,0,0,_IMR7
.align 1
_IGDBL:
.SYMDEF "_IGDBL" REG:2,26,LEN:1
ds 1
.stabs "IGDBL:S14",40,0,0,_IGDBL
.align 1
_IGDBH:
.SYMDEF "_IGDBH" REG:2,25,LEN:1
ds 1
.stabs "IGDBH:S14",40,0,0,_IGDBH
.align 1
_IRSR2:
.SYMDEF "_IRSR2" REG:2,22,LEN:1
ds 1
.stabs "IRSR2:S14",40,0,0,_IRSR2
.align 1
_IRSR1:
.SYMDEF "_IRSR1" REG:2,21,LEN:1
ds 1
.stabs "IRSR1:S14",40,0,0,_IRSR1
.align 1
_SFR7:
.SYMDEF "_SFR7" REG:2,20,LEN:1
ds 1
.stabs "SFR7:S14",40,0,0,_SFR7
.align 1
_WUCR4:
.SYMDEF "_WUCR4" REG:2,18,LEN:1
ds 1
.stabs "WUCR4:S14",40,0,0,_WUCR4
.align 1
_TM2DAL:
.SYMDEF "_TM2DAL" REG:2,16,LEN:1
ds 1
.stabs "TM2DAL:S14",40,0,0,_TM2DAL
.align 1
_TM2DAH:
.SYMDEF "_TM2DAH" REG:2,15,LEN:1
ds 1
.stabs "TM2DAH:S14",40,0,0,_TM2DAH
.align 1
_TM2DBL:
.SYMDEF "_TM2DBL" REG:2,14,LEN:1
ds 1
.stabs "TM2DBL:S14",40,0,0,_TM2DBL
.align 1
_TM2DBH:
.SYMDEF "_TM2DBH" REG:2,13,LEN:1
ds 1
.stabs "TM2DBH:S14",40,0,0,_TM2DBH
.align 1
_TM2CR2:
.SYMDEF "_TM2CR2" REG:2,12,LEN:1
ds 1
.stabs "TM2CR2:S14",40,0,0,_TM2CR2
.align 1
_TM2CR1:
.SYMDEF "_TM2CR1" REG:2,11,LEN:1
ds 1
.stabs "TM2CR1:S14",40,0,0,_TM2CR1
.align 1
_TM1DAL:
.SYMDEF "_TM1DAL" REG:2,10,LEN:1
ds 1
.stabs "TM1DAL:S14",40,0,0,_TM1DAL
.align 1
_TM1DAH:
.SYMDEF "_TM1DAH" REG:2,9,LEN:1
ds 1
.stabs "TM1DAH:S14",40,0,0,_TM1DAH
.align 1
_TM1DBL:
.SYMDEF "_TM1DBL" REG:2,8,LEN:1
ds 1
.stabs "TM1DBL:S14",40,0,0,_TM1DBL
.align 1
_TM1DBH:
.SYMDEF "_TM1DBH" REG:2,7,LEN:1
ds 1
.stabs "TM1DBH:S14",40,0,0,_TM1DBH
.align 1
_TM1CR2:
.SYMDEF "_TM1CR2" REG:2,6,LEN:1
ds 1
.stabs "TM1CR2:S14",40,0,0,_TM1CR2
.align 1
_TM1CR1:
.SYMDEF "_TM1CR1" REG:2,5,LEN:1
ds 1
.stabs "TM1CR1:S14",40,0,0,_TM1CR1
.align 1
_TBWAH:
.SYMDEF "_TBWAH" REG:1,79,LEN:1
ds 1
.stabs "TBWAH:S14",40,0,0,_TBWAH
.align 1
_TBWAL:
.SYMDEF "_TBWAL" REG:1,78,LEN:1
ds 1
.stabs "TBWAL:S14",40,0,0,_TBWAL
.align 1
_TBWCR:
.SYMDEF "_TBWCR" REG:1,77,LEN:1
ds 1
.stabs "TBWCR:S14",40,0,0,_TBWCR
.align 1
_PCH:
.SYMDEF "_PCH" REG:1,72,LEN:1
ds 1
.stabs "PCH:S14",40,0,0,_PCH
.align 1
_STKMON:
.SYMDEF "_STKMON" REG:1,71,LEN:1
ds 1
.stabs "STKMON:S14",40,0,0,_STKMON
.align 1
_TBPTH:
.SYMDEF "_TBPTH" REG:1,70,LEN:1
ds 1
.stabs "TBPTH:S14",40,0,0,_TBPTH
.align 1
_TBPTL:
.SYMDEF "_TBPTL" REG:1,69,LEN:1
ds 1
.stabs "TBPTL:S14",40,0,0,_TBPTL
.align 1
_FLKR:
.SYMDEF "_FLKR" REG:1,68,LEN:1
ds 1
.stabs "FLKR:S14",40,0,0,_FLKR
.align 1
_EERD:
.SYMDEF "_EERD" REG:1,67,LEN:1
ds 1
.stabs "EERD:S14",40,0,0,_EERD
.align 1
_EERA:
.SYMDEF "_EERA" REG:1,66,LEN:1
ds 1
.stabs "EERA:S14",40,0,0,_EERA
.align 1
_EECR2:
.SYMDEF "_EECR2" REG:1,65,LEN:1
ds 1
.stabs "EECR2:S14",40,0,0,_EECR2
.align 1
_EECR1:
.SYMDEF "_EECR1" REG:1,64,LEN:1
ds 1
.stabs "EECR1:S14",40,0,0,_EECR1
.align 1
_URRDH:
.SYMDEF "_URRDH" REG:1,55,LEN:1
ds 1
.stabs "URRDH:S14",40,0,0,_URRDH
.align 1
_URRDL:
.SYMDEF "_URRDL" REG:1,54,LEN:1
ds 1
.stabs "URRDL:S14",40,0,0,_URRDL
.align 1
_URTD:
.SYMDEF "_URTD" REG:1,53,LEN:1
ds 1
.stabs "URTD:S14",40,0,0,_URTD
.align 1
_URS:
.SYMDEF "_URS" REG:1,52,LEN:1
ds 1
.stabs "URS:S14",40,0,0,_URS
.align 1
_URCR:
.SYMDEF "_URCR" REG:1,51,LEN:1
ds 1
.stabs "URCR:S14",40,0,0,_URCR
.align 1
_P6ODCR:
.SYMDEF "_P6ODCR" REG:1,18,LEN:1
ds 1
.stabs "P6ODCR:S14",40,0,0,_P6ODCR
.align 1
_P5ODCR:
.SYMDEF "_P5ODCR" REG:1,17,LEN:1
ds 1
.stabs "P5ODCR:S14",40,0,0,_P5ODCR
.align 1
_P6HDSCR:
.SYMDEF "_P6HDSCR" REG:1,15,LEN:1
ds 1
.stabs "P6HDSCR:S14",40,0,0,_P6HDSCR
.align 1
_P5HDSCR:
.SYMDEF "_P5HDSCR" REG:1,14,LEN:1
ds 1
.stabs "P5HDSCR:S14",40,0,0,_P5HDSCR
.align 1
_P6PLCR:
.SYMDEF "_P6PLCR" REG:1,12,LEN:1
ds 1
.stabs "P6PLCR:S14",40,0,0,_P6PLCR
.align 1
_P5PLCR:
.SYMDEF "_P5PLCR" REG:1,11,LEN:1
ds 1
.stabs "P5PLCR:S14",40,0,0,_P5PLCR
.align 1
_P6PHCR:
.SYMDEF "_P6PHCR" REG:1,9,LEN:1
ds 1
.stabs "P6PHCR:S14",40,0,0,_P6PHCR
.align 1
_P5PHCR:
.SYMDEF "_P5PHCR" REG:1,8,LEN:1
ds 1
.stabs "P5PHCR:S14",40,0,0,_P5PHCR
.align 1
_ADCVH:
.SYMDEF "_ADCVH" REG:0,70,LEN:1
ds 1
.stabs "ADCVH:S14",40,0,0,_ADCVH
.align 1
_ADCVL:
.SYMDEF "_ADCVL" REG:0,69,LEN:1
ds 1
.stabs "ADCVL:S14",40,0,0,_ADCVL
.align 1
_ADDH:
.SYMDEF "_ADDH" REG:0,68,LEN:1
ds 1
.stabs "ADDH:S14",40,0,0,_ADDH
.align 1
_ADDL:
.SYMDEF "_ADDL" REG:0,67,LEN:1
ds 1
.stabs "ADDL:S14",40,0,0,_ADDL
.align 1
_ADER1:
.SYMDEF "_ADER1" REG:0,65,LEN:1
ds 1
.stabs "ADER1:S14",40,0,0,_ADER1
.align 1
_ADISR:
.SYMDEF "_ADISR" REG:0,64,LEN:1
ds 1
.stabs "ADISR:S14",40,0,0,_ADISR
.align 1
_ADCR2:
.SYMDEF "_ADCR2" REG:0,63,LEN:1
ds 1
.stabs "ADCR2:S14",40,0,0,_ADCR2
.align 1
_ADCR1:
.SYMDEF "_ADCR1" REG:0,62,LEN:1
ds 1
.stabs "ADCR1:S14",40,0,0,_ADCR1
.align 1
_SPIW:
.SYMDEF "_SPIW" REG:0,57,LEN:1
ds 1
.stabs "SPIW:S14",40,0,0,_SPIW
.align 1
_SPIR:
.SYMDEF "_SPIR" REG:0,56,LEN:1
ds 1
.stabs "SPIR:S14",40,0,0,_SPIR
.align 1
_SPIS:
.SYMDEF "_SPIS" REG:0,55,LEN:1
ds 1
.stabs "SPIS:S14",40,0,0,_SPIS
.align 1
_SPICR:
.SYMDEF "_SPICR" REG:0,54,LEN:1
ds 1
.stabs "SPICR:S14",40,0,0,_SPICR
.align 1
_WDTCR:
.SYMDEF "_WDTCR" REG:0,33,LEN:1
ds 1
.stabs "WDTCR:S14",40,0,0,_WDTCR
.align 1
_IMR6:
.SYMDEF "_IMR6" REG:0,32,LEN:1
ds 1
.stabs "IMR6:S14",40,0,0,_IMR6
.align 1
_IMR4:
.SYMDEF "_IMR4" REG:0,30,LEN:1
ds 1
.stabs "IMR4:S14",40,0,0,_IMR4
.align 1
_IMR2:
.SYMDEF "_IMR2" REG:0,28,LEN:1
ds 1
.stabs "IMR2:S14",40,0,0,_IMR2
.align 1
_IMR1:
.SYMDEF "_IMR1" REG:0,27,LEN:1
ds 1
.stabs "IMR1:S14",40,0,0,_IMR1
.align 1
_SFR6:
.SYMDEF "_SFR6" REG:0,25,LEN:1
ds 1
.stabs "SFR6:S14",40,0,0,_SFR6
.align 1
_SFR4:
.SYMDEF "_SFR4" REG:0,23,LEN:1
ds 1
.stabs "SFR4:S14",40,0,0,_SFR4
.align 1
_SFR2:
.SYMDEF "_SFR2" REG:0,21,LEN:1
ds 1
.stabs "SFR2:S14",40,0,0,_SFR2
.align 1
_SFR1:
.SYMDEF "_SFR1" REG:0,20,LEN:1
ds 1
.stabs "SFR1:S14",40,0,0,_SFR1
.align 1
_WUCR3:
.SYMDEF "_WUCR3" REG:0,18,LEN:1
ds 1
.stabs "WUCR3:S14",40,0,0,_WUCR3
.align 1
_WUCR2:
.SYMDEF "_WUCR2" REG:0,17,LEN:1
ds 1
.stabs "WUCR2:S14",40,0,0,_WUCR2
.align 1
_WUCR1:
.SYMDEF "_WUCR1" REG:0,16,LEN:1
ds 1
.stabs "WUCR1:S14",40,0,0,_WUCR1
.align 1
_EIESCR:
.SYMDEF "_EIESCR" REG:0,15,LEN:1
ds 1
.stabs "EIESCR:S14",40,0,0,_EIESCR
.align 1
_OMCR:
.SYMDEF "_OMCR" REG:0,14,LEN:1
ds 1
.stabs "OMCR:S14",40,0,0,_OMCR
.align 1
_IOCR6:
.SYMDEF "_IOCR6" REG:0,12,LEN:1
ds 1
.stabs "IOCR6:S14",40,0,0,_IOCR6
.align 1
_IOCR5:
.SYMDEF "_IOCR5" REG:0,11,LEN:1
ds 1
.stabs "IOCR5:S14",40,0,0,_IOCR5
.align 1
_PORT6:
.SYMDEF "_PORT6" REG:0,6,LEN:1
ds 1
.stabs "PORT6:S14",40,0,0,_PORT6
.align 1
_PORT5:
.SYMDEF "_PORT5" REG:0,5,LEN:1
ds 1
.stabs "PORT5:S14",40,0,0,_PORT5
.align 1
_RSR:
.SYMDEF "_RSR" REG:0,4,LEN:1
ds 1
.stabs "RSR:S14",40,0,0,_RSR
.align 1
_R4:
.SYMDEF "_R4" REG:0,4,LEN:1
ds 1
.stabs "R4:S14",40,0,0,_R4
.align 1
_STATUS:
.SYMDEF "_STATUS" REG:0,3,LEN:1
ds 1
.stabs "STATUS:S14",40,0,0,_STATUS
.align 1
_R3:
.SYMDEF "_R3" REG:0,3,LEN:1
ds 1
.stabs "R3:S14",40,0,0,_R3
.align 1
_PCL:
.SYMDEF "_PCL" REG:0,2,LEN:1
ds 1
.stabs "PCL:S14",40,0,0,_PCL
.align 1
_R2:
.SYMDEF "_R2" REG:0,2,LEN:1
ds 1
.stabs "R2:S14",40,0,0,_R2
.align 1
_BSR:
.SYMDEF "_BSR" REG:0,1,LEN:1
ds 1
.stabs "BSR:S14",40,0,0,_BSR
.align 1
_R1:
.SYMDEF "_R1" REG:0,1,LEN:1
ds 1
.stabs "R1:S14",40,0,0,_R1
.align 1
_IAR:
.SYMDEF "_IAR" REG:0,0,LEN:1
ds 1
.stabs "IAR:S14",40,0,0,_IAR
.align 1
_R0:
.SYMDEF "_R0" REG:0,0,LEN:1
ds 1
.stabs "R0:S14",40,0,0,_R0
.section ".code"
end
